This invention relates to a semiconductor memory device, and, more particularly, to a semiconductor memory device in which the signal transmission speed is improved between the memory cells and/or decoder circuit and the control circuits, such as buffer circuits and various logic circuits, if any.
A semiconductor memory device includes: bonding pads for receiving input signals; various kinds of buffer circuits such as an address buffer circuit, a write-in buffer circuit, a read-out buffer circuit, the major function of which is to amplify the signals received by or generated in the semiconductor memory device; possibly some logic circuits for miscelleneous purposes and a decoder circuit for decoding the signals or transforming the format of the signals and memory cells.
One of the essential requirements for memory devices is the improvement of transmission speed of signals in the memory devices, a requirement predominantly determined by the time constant or the product of resistance and capacitance. Therefore, reduction in resistance is one of the important requirements for semiconductor memory devices. Higher grade of integration is another of the important requirements for semiconductor memory devices. Because of these factors, the layout of each ingredient constituting a semiconductor memory device is an important parameter for design of a semiconductor memory device.
FIG. 1 illustrates an exemplary layout of each ingredient constituting a semiconductor memory device available in the prior art. Referring to FIG. 1, the illustrated layout features a ground line (GND) 7 placed along the external edges of a semiconductor memory device 1 and surrounds various control circuits 4, such as an address buffer circuit, a write-in buffer circuit and a read-out buffer circuit, and logic circuits. These control circuits further surround an electric power supply line (Vcc) 6, which surrounds a group of signal lines 5, each of which connects various of the control circuits 4 with each other. The signal lines 5 finally surround memory cell areas 2 and decoder circuit 3, which are placed at the center of the semiconductor memory device 1.
The major advantage of this conventional layout illustrated in FIG. 1 is that no crossing of the electric power supply line (Vcc) 6 and the ground line (GND) 7 is required, both of which have a relatively large current capacity. Thus, there is no requirement for a so-called "bridge" between these two lines. A "bridge" is a structure in which one line crosses under the other line via a diffusion layer formed in the substrate, or one line crosses over the other line with an insulator layer therebetween. Diffusion and insulating layers are effective in avoiding a voltage drop inevitable in a bridge, thus further excluding a possibility of malfunctions caused by the voltage drop. However, this conventional layout illustrated in FIG. 1 inevitably includes a considerable number of the so-called bridges between the memory cell areas 2 and decoder circuit 3, both of which are placed at the center of the memory device 1, and the control circuits 4, such as buffer circuits and logic circuits, which are located around the cell areas and circuits 2 and 3, and between the control circuits 4 and the bonding pads which are placed along the edges of the semiconductor memory device 1.
These so-called bridges are included in the category of multi-layered connections. Multi-layered connections usually cause a considerable magnitude of increase in resistance in the line in which they are found. This increase in resistance, in combination with capacitance which is inevitable for a semiconductor memory device, causes a considerable magnitude of increase in time constant, further resulting in a considerable magnitude of increase in delay of signal transmission. Due to the nature of memory devices, a slow signal transmission speed is undesired especially for lines connecting the control circuits, particularly the buffer circuits and the decoder circuit or for output signal lines connecting the memory cells and the output bonding pads.